This invention is generally related to the design of Very Large Scale Integrated Circuit (VLSI) chips and, more particularly, to a method for performing a physical verification of the integrated circuit (IC) layout design.
Physical verification is typically divided into three areas: i) design rules checking, ii) circuit extraction and layout to be compared against a corresponding schematic representation, and iii) parasitic parameter extraction. Of particular interest is finding how the circuit extraction and layout are applied against a schematic (LVS) representation of a multi-fingered MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor) layout to improve the confidence level of the physical verification process. Ultimately, the LVS comparison verifies the device layout properties and connectivity against circuit schematics.
As the integration of semiconductor process technology progresses with sub-100 nm lithography and 300 mm multi-part number wafers, the investment for processed wafers demands an increased level of confidence that the physical circuit layouts, (i.e., sets of drawings containing coordinates of rectangles drawn in different layers used to generate the masks for integrated circuit manufacturing) match the intended circuit schematic designs. The schematic or netlist of the circuit is simulated on a Computer Aided Design (CAD) tool to verify the circuit functionality.
A semiconductor integrated circuit layout, including the dimensional accuracy of the pattern shapes, must be efficiently verified with high level of accuracy. The method and the algorithm defining this process provide the aforementioned layout versus schematic verification.
A significant number of patents and publications exist that relate to the physical verification of integrated circuit designs. Typically, only the MOS transistor channel length (L), the channel width (W) or channel width per finger (WF), and the number of fingers (NF) are checked, a process that is globally referred to as flat layout extraction. The aforementioned features are deemed to be the most basic features of the MOS transistor at a level that cannot be broken down any further. This approach is illustrated in FIGS. 1 and 2 as they apply, respectively, to a single finger and to a multi-finger layout. In the invention to be described hereinafter, the channel width of a single finger transistor will be denoted, for sake of simplicity, by the referenced nomenclature WF. In both figures, NF matches the number of gates 110. The prior art that utilizes a layout versus schematic comparison in a hierarchical methodology only applies to a logic gate level design but not to a transistor level design. In contrast, at the transistor level, as will be described hereinafter in the Detailed Description of the Invention, circuits will be broken down into sub-circuits, the sub-circuit consisting of a set of basic circuit elements, such as transistors, resistors, capacitors, and the like, with their corresponding interconnections wherein the combination of such circuit elements does not perform an electrical function. Accordingly, a typical hierarchical structure will consist of basic independent circuit elements, followed by the aforementioned sub-circuits, by a circuit, logic, and the like.
A conventional IC layout extraction and LVS process are shown by way of the prior art flow chart illustrated in FIG. 3. No MOS transistor source and drain diffusion dimensions can be checked when using a flat extraction. It is known in the art that the dimensions of the source and drain diffusion are critical parameters in contemporary VLSI chip designs because the impact of the source and drain parasitic capacitances of the transistor increases dramatically as the transistor feature size is scaled downward. These parasitic capacitances are fully dependent on the dimensions of the source and drain diffusion. As a result, what is needed is a detailed comparison of the layout versus the schematic check that also includes checking the source and drain dimensions. The performance of the circuit being manufactured may deviate significantly from the design target specifications because differences between the physical layout and the circuit schematic are not fully checked. The dimensions of the source and drain diffusion, referenced as “DIFFL”, “DIFFM”, and “DIFFR” are illustrated in FIG. 4, and are intended to be examples of layout features which can be checked by utilizing the device sub-circuit based extraction method to perform LVS. Also shown therein are three layers referred to “Multi” (410), “Left” (420), and “Right” (430). This cannot be achieved by way of a conventional flat extraction method. As the semiconductor industry continues scaling down the size of the device features to the nanometer region, other transistor geometric parameters such as gate shapes, number of source/drain/gate contacts, and other hybrid devices, e.g., interdigitated differential pairs, will also be required to be checked by way of LVS. The inventive method to be described hereinafter is intended to become a generic method to perform a complete LVS checking for any VLSI design based on the sub-circuit based extraction algorithm.
In three related patents, U.S. Pat. No. 5,831,316, U.S. Pat. No. 5,789,791, and U.S. Pat. No. 6,404,030, a multi-finger MOS transistor layout is described. Comparing the single finger MOS transistor layout shown in FIG. 1, the multi-finger transistor layout shown in FIG. 2 breaks the MOS transistor layout into basic shapes which are placed in parallel with the proper wiring connections (not shown).
U.S. Pat. No. 5,831,316 describes a method of equally positioning the source and drain regions between multi-gates, the base resistance values of parasitic bipolar transistors in each finger MOS being equal to each other. Thus, each finger MOS transistor in the multi-finger MOS transistor is turned on simultaneously to enhance the electrostatic discharge (ESD) protection performance. In the analog and mixed signal circuit domain, the gate resistance of a MOS transistor is one major factor affecting the high frequency performance.
U.S. Pat. No. 5,789,791 describes how the gate resistance of a high-frequency multi-finger MOS transistor is reduced by shorting the ends of each of the gates by utilizing gate contacts, metal regions, vias, and a metal layer.
U.S. Pat. No. 6,404,030 describes the high frequency performance of a MOS transistor which is improved by linking the gates and by forming conductive vias in each gate finger. Therefore, the multi-finger strategy is preferred since it improves the performance of the device by reducing the gate resistance, equalizing the turn-on of each single finger MOS transistor and reducing the area occupied by the MOS transistor. This consideration has long dominated modem IC designs.
U.S. Pat. No. 6,009,252 describes a method for determining equivalencies between integrated circuit schematics and layouts using color symmetrizing matrices. The color symmetrizing matrices that are generated correspond to respective ‘child cells’ in the circuit schematic. Child cells are characterized by having a number of symmetrical configurations that are electrically equivalent at the port level. The definition of child cells is advantageously used for a hierarchical LVS comparison algorithm. However, two electrically equivalent child cells may be matched inappropriately if the detailed cell attributes are not fully extracted and compared. In most cases, the channel length and width and the number of fingers are attributes to be extracted and compared in a flat extraction and LVS process. Other device attributes, such as the dimensions of the source and drain diffusions, the number of source to drain and drain to gate contacts, and the like, are not extracted and compared altogether. For way of example, FIGS. 5a–5b show transistor and layouts having different geometric dimensions. Explicitly, the dimensions of the source to drain diffusions 120, 130, and 220 differ between (a) and (b) while the channel length L (equal to L0), channel width WF (equal to W0), and number of fingers NF (=3) coincide for both transistors. In the prior art, the extraction and LVS is achieved by extracting L, WF, and NF and comparing these parameters against a schematic netlist that includes among others, a flat model element with L=L0, WF=W0, and NF=3 fully defined. This results in the transistors shown in FIGS. 5a–5b to be successfully matched to an identical schematic cell inappropriately because it is based on a presumption that the two transistors, i.e., FIG. 5a and 5b match each other, which, is incorrect. This is due to information of source and drain diffusion dimensions (DIFFL, DIFFM, and DIFFR) missing in the LVS comparison process.
U.S. Pat. No. 5,712,794 describes an automated method for adding attributes identified on a circuit schematic diagram to an integrated circuit layout. Even though the process of adding an attribute or property of a device can be automated, no mention is made in this patent or other references on how to check the correctness of the added attribute.
Although flat MOS transistor modeling has been used for many decades and it is known that it runs the fastest, it lacks the flexibility and accuracy of a parameterized sub-circuit modeling. The use of sub-circuit models, which are hierarchical models based on flat FET models with technology specific elements and parameters added, has become a standard practice in industry. The parameterized sub-circuit models not only supports useful features such as statistical analysis, but they also increase the accuracy because of additional components such as gate resistance, gate tunneling current, number of device fingers, etc. Examples of features that can be added are: i) Additional circuit elements such as gate resistance, gate to source and drain tunneling current, and a modified body resistance; ii) Geometrical layout parameters so that the dimensions of the transistor can be specified in a more natural way; iii) New instance parameters such as a new set of device dimensions, a different number of device fingers or number of body contacts; iv) Instances when model parameterization can also be applied locally to a sub-circuit, such that local statistical supporting analysis of neighboring device variations can, likewise, be included; and v) Cases where the sub-circuit also allows adding customized features to the model.
Other related references are:
An article by M. Lee, R. B. Anna, Jui-Chu Lee, S. M. Parker, K. M. Newton entitled “A scalable BSIM3v3 RF model for multi-finger NMOSFETs with ring substrate contact”, published in the 2002 IEEE International Symposium on Circuits and Systems, Vol. 5, May 2002, pp 221–224, there is described a scalable RF (Radio Frequency) sub-circuit MOS transistor model using a commercial modeling tool to support a simple RC (Resistance and Capacitance) substrate network with well defined intrinsic parasitic parameters for Scattering Parameter (also referred to as an S-parameter, a common measure in RF technology) scalability. It is claimed that using a sub-circuit modeling strategy provides accurate and scalable modeling capability for high performance RF circuit design.
A gate level sub-circuit extraction algorithm is described in an article by W.-H. Chang, S. D. Tzeng, C. Y. Lee, entitled “A novel sub-circuit extraction algorithm by recursive identification scheme”, published in the 2001 IEEE International Symposium on Circuits and Systems, Vol. 5, May 2001, pp 491–494. Based on a recursive graph identification scheme, the proposed sub-circuit extraction algorithm can decrease the run time significantly and is technology independent.
Articles by N. Vijaykrishnan, N. Ranganathan, entitled “SUBGEN: a genetic approach for sub-circuit extraction”, published in the 1996 Ninth International Conference VLSI Design, January 1996, Pages: 343–345 and by Z. Ling, D. Y. Y. Yun, entitled “An efficient sub-circuit extraction algorithm by resource management”, published in the 1996 Second International Conference on ASIC, October 1996, pp. 9–14, describes a sub-circuit extraction algorithm to identify a sub-circuit in a large scale integrated circuit layout. The algorithm described by N. Vijaykrishnan et al. begins with a random population potential match and details a so-called genetic representation algorithm. In the paper by Z. Ling et al., an efficient approach is described to solve the subgraph isomorphism problem based on the resource management paradigm is transformed to extract sub-circuit.
An article by G. Yokomizo, C. Yoshida, M. Miyama, Y. Motono, K. Nakajo, entitled “A new circuit recognition and reduction method for pattern based circuit simulation”, published in the 1990 IEEE Custom Integrated Circuits Conference, May 1990, pp. 9.4/1–9.4/4, a circuit recognition and reduction method to extract sub-circuit data corresponding to the critical path is described. When including all relevant parasitics and internal loading, the critical path can be optimized and the design can be improved substantially.
Comparing the combined methods described by W.-H. Chang et al., N. Vijaykrishnan et al., Z. Ling et al., to the method described by Yokomizo et al., the latter takes one more step, i.e., the circuit reduction, to further simplify the extracted sub-circuit when finding a critical path. However, the sub-circuit described in the combined publications is a combination of several MOS transistors and/or resistors, etc., but not a transistor level representation that can be used to improve the geometric property comparison accuracy.
Finally, the article by W. Kim, H. Shin, entitled “Hierarchical LVS based on hierarchy rebuilding” and published in the 1998 Design Automation Conference. February 1998, pp. 379–384, described a method for extracting sub-circuit(s) from a VLSI design and then performing layout versus schematic comparison hierarchically. Experimental results show that this technique is effective and efficient regarding CPU time and memory usage. Once again, since the sub-circuit usage at the transistor level is not suggested, the hierarchical LVS only provides increased accuracy and efficiency on the circuit connectivity verification. Increasing the accuracy of device property checking can only be achieved by using the sub-circuit based LVS method as proposed in this invention, where each critical property or parameter in a transistor sub-circuit level has to be compared and matched.
The typical prior art flat extraction method is described below. Referring back to prior art FIG. 1 there is shown a flat modeled single finger MOS transistor layout. The extraction obtains the gate pattern and node from the interaction of polysilicon gate 110 and active region 140. The source and drain (120 and 130, swappable) are then extracted by the difference of 140 and 110. Then the extracted netlist can be written as Netlist (1).T1 (GNode, SNode, DNode) model=NMOS L=L0, W=W0,  (1)where T1 is a sequence name of the transistor observing a particular naming rule in a particular electronic design tool. Each electrical node is defined in parenthesis where GNode represents Gate, SNode for Source and DNode for Drain. Since the electrical connectivity extraction and checking is not within the scope of the invention, it is assumed that the electrical nodes of the gate, source, and drain of the MOS transistor will be referred to as GNode, SNode, and DNode, respectively. The node definitions in parenthesis are followed by “model=” and “NMOS”, which is the model name of the extracted transistor, i.e., a flat model or sub-circuit model. The device properties of channel length (L) and channel width (WF) are calculated and listed accordingly. After the netlist is generated and the properties extracted, LVS is initiated to compare the node connections and property values. In the present case, only the channel length and width will be compared against the design schematic values.
Referring now back to FIG. 2, there is shown a multi-finger layout where three polysilicon gate fingers 110 break the entire active diffusion 140 in four sections, 120, two of 220, and 130. Another horizontal polysilicon bar 210 joins the three fingers 110, making the three gate fingers transistor wired as one. In case of a multi-finger layout, a conventional method extracts three MOS transistors as Netlists (2)–(4), i.e.,T2 (GNode, SNode, DNode) model=NMOS L=L0, WF=W0  (2)T3 (GNode, SNode, DNode) model=NMOS L=L0, WF=W0  (3)T4 (GNode, SNode, DNode) model=NMOS L=L0, WF=W0  (4)
The extracted transistors look exactly the same to each other except for different notation names. Usually, after the primitive extraction, most LVS tools perform a reduction process intended to merge all the devices connected in parallel (the source and drain wiring are not shown) to one device. In this case, the final extracted netlist will be like Netlist (5).T5 (GNode, SNode, DNode) model=NMOS L=L0, W=Wall,  (5)where Wall=3W0, since the three devices are in parallel. It will be noticed that, in both examples, critical model properties such as the number of fingers (NF) are not extracted and compared. Moreover, it is not possible to compare additional device features such as diffusion segment dimensions, which typically have a significant impact on the device and circuit performance.
The problem solved by the invention is that LVS checks all the layout geometric parameters after performing a sub-circuit based extraction. The prior art for the general layout physical verification process is shown in FIG. 3. The layout extraction and LVS process (310) need to be performed after the layout is completed. If the comparison shows that the layout is correct, i.e., the extracted netlist is equivalent to the schematic netlist, the physical verification branches to the “parasitic extraction” stage 360. When the post-layout simulation results satisfy the design specification, the complete physical verification process is terminated and is followed by the tape-out process (i.e., formalizing a verified layout and readying it for mask generation).
As shown in FIG. 3, present solutions typically only recognize devices as a group of flat basic components like resistors and single finger MOS transistors represented by “Flat extraction” 320. In addition to breaking the design coherence with the schematic by recognizing a single device as multiple primitive elements, this practice leads to simulation inefficiencies downstream requiring an iterative solution of multiple elements instead of a single sub-circuit device model. Simulation efficiency may be improved by merging the primitive elements, as discussed above for Netlist (5), but important structural details may be lost in the merge. This practice only partially works for a multi-finger layout because the critical device property “number of fingers” cannot be checked. The single finger device of FIG. 1 and the three-finger device of FIG. 2 after reduction achieves the same result as Netlist (5) even though individually they perform differently from one another. Certain advanced algorithms handle the property “number of fingers” by using a multiplicity factor but no other geometric parameters, such as source and drain diffusion dimensions are extracted and compared during LVS. No known solution has been disclosed to solve the general layout geometric parameter extraction and LVS.
In summary, LVS is a critical step in the physical verification phase of the IC design process. Known solutions cannot extract a complete list of geometric parameters of a transistor and perform a complete parametric and connectivity verification. The invention solves this problem by incorporating three additional marking layers and utilizing a sub-circuit based extraction algorithm to extract a complete list of transistor geometric parameters. Followed by the sub-circuit based LVS method, the stated shortage of current extraction and LVS is resolved, resulting in an improved match of the IC layout to the design specification.